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Searched refs:DDRC_ZQCTL1 (Results 1 – 6 of 6) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c37 { DDRC_ZQCTL1(0), 0x028061A8 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c37 { DDRC_ZQCTL1(0), 0x028061A8 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c46 { DDRC_ZQCTL1(0), 0x028061A8 },
A Dlpddr4_timing.c44 { DDRC_ZQCTL1(0), 0x028061A8 },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg91 /* DDRC_ZQCTL1 */
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h432 #define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) macro

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