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Searched refs:DDRPHYC (Results 1 – 4 of 4) sorted by relevance

/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32mp1-ddr.txt1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
7 - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
166 <&rcc_clk DDRPHYC>,
/u-boot/include/dt-bindings/clock/
A Dstm32mp1-clks.h240 #define DDRPHYC 224 macro
/u-boot/arch/arm/dts/
A Dstm32mp15-u-boot.dtsi55 <&rcc DDRPHYC>,
/u-boot/drivers/clk/
A Dclk_stm32mp1.c519 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
2141 case DDRPHYC: in stm32mp1_clk_set_rate()

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