Searched refs:DDR_PLL_CONFIG_OUT_DIV_VAL1 (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A D	clk.c	167 #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) macro 267 ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL1); in qca956x_pll_init()

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