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Searched refs:DDR_PLL_CONFIG_PLLPWD_MASK (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c78 #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000 macro
80 (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
264 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(1)); in qca956x_pll_init()
289 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0)); in qca956x_pll_init()

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