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Searched refs:DDR_TIMING_CFG_2 (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/configs/
A Dls1021atsn.h32 #define DDR_TIMING_CFG_2 0x0040d120 macro
A Dls1021aiot.h34 #define DDR_TIMING_CFG_2 0x0040d120 macro
A Dls1021atwr.h33 #define DDR_TIMING_CFG_2 0x0040d120 macro
/u-boot/board/freescale/ls1021aiot/
A Dls1021aiot.c63 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
/u-boot/board/freescale/ls1021atsn/
A Dls1021atsn.c41 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
/u-boot/board/freescale/ls1021atwr/
A Dls1021atwr.c157 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()

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