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Searched refs:DDR_TIMING_CFG_4 (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/configs/
A Dls1021atsn.h34 #define DDR_TIMING_CFG_4 0x00000001 macro
A Dls1021aiot.h36 #define DDR_TIMING_CFG_4 0x00000001 macro
A Dls1021atwr.h35 #define DDR_TIMING_CFG_4 0x00000001 macro
/u-boot/board/freescale/ls1021aiot/
A Dls1021aiot.c65 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
/u-boot/board/freescale/ls1021atsn/
A Dls1021atsn.c43 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
/u-boot/board/freescale/ls1021atwr/
A Dls1021atwr.c159 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()

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