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Searched refs:DEBUG_WR_REG (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-mvebu/serdes/axp/
A Dhigh_speed_env_lib.c645 DEBUG_WR_REG(SOC_CTRL_REG, tmp); in serdes_phy_config()
1043 DEBUG_WR_REG(PEX_DBG_CTRL_REG in serdes_phy_config()
1108 DEBUG_WR_REG(SATA_BASE_REG in serdes_phy_config()
1117 DEBUG_WR_REG(SATA_BASE_REG in serdes_phy_config()
1149 DEBUG_WR_REG(MV_ETH_REGS_BASE in serdes_phy_config()
1158 DEBUG_WR_REG(MV_ETH_REGS_BASE in serdes_phy_config()
1171 DEBUG_WR_REG in serdes_phy_config()
1178 DEBUG_WR_REG in serdes_phy_config()
1203 DEBUG_WR_REG(SOC_CTRL_REG, tmp); in serdes_phy_config()
1338 DEBUG_WR_REG in serdes_phy_config()
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/u-boot/drivers/ddr/marvell/a38x/
A Dddr_ml_wrapper.h38 #define DEBUG_WR_REG(reg, val) \ macro
48 #define DEBUG_WR_REG(reg, val) macro
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_init.h33 #define DEBUG_WR_REG(reg, val) \ macro
43 #define DEBUG_WR_REG(reg, val) macro
/u-boot/arch/arm/mach-mvebu/serdes/a38x/
A Dctrl_pex.c179 DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); in hws_pex_config()
185 DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp); in hws_pex_config()

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