Searched refs:DPLL (Results 1 – 11 of 11) sorted by relevance
| /u-boot/drivers/clk/ti/ |
| A D | Kconfig | 7 bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"
10 This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3308.c | 61 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
118 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_pll_rate()
119 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
207 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
208 priv->cru, DPLL); in rk3308_mac_set_clk()
798 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_rate()
799 priv->cru, DPLL); in rk3308_clk_get_rate()
873 ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru, in rk3308_clk_set_rate()
874 DPLL, rate); in rk3308_clk_set_rate()
875 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_set_rate()
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| A D | clk_rk3368.c | 152 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
310 rkclk_set_pll(cru, DPLL, dpll_cfg); in rk3368_ddr_set_clk()
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| A D | clk_px30.c | 1177 rate = px30_clk_get_pll_rate(priv, DPLL); in px30_clk_get_rate()
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| /u-boot/arch/arm/mach-exynos/include/mach/ |
| A D | clk.h | 19 #define DPLL 9 macro
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| /u-boot/include/dt-bindings/clock/ |
| A D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3368.h | 17 DPLL, enumerator
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| A D | cru_px30.h | 25 DPLL, enumerator
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| /u-boot/board/rockchip/evb_rv1108/ |
| A D | README | 37 APLL: 600000000 DPLL:792000000 GPLL:384000000
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| /u-boot/arch/arm/include/asm/arch-rk3308/ |
| A D | cru_rk3308.h | 33 DPLL, enumerator
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| /u-boot/arch/arm/mach-exynos/ |
| A D | clock.c | 1050 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
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