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Searched refs:DRAMTMG2_TWR2RD (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dddr3_1333.c63 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
A Dlpddr3_stock.c59 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
A Dddr2_v3s.c60 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sunxi_dw.h166 #define DRAMTMG2_TWR2RD(x) ((x) << 0) macro

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