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Searched refs:DRAMTMG5_TCKSRE (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dddr3_1333.c69 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
A Dlpddr3_stock.c65 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
A Dddr2_v3s.c66 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sunxi_dw.h178 #define DRAMTMG5_TCKSRE(x) ((x) << 16) macro

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