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Searched refs:DRAM_PHY_CFG_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_regs.h272 #define DRAM_PHY_CFG_REG 0x15ec macro
A Dddr3_training.c430 DRAM_PHY_CFG_REG, 0x28, 0x3e)); in hws_ddr3_tip_init_controller()
435 DRAM_PHY_CFG_REG, 0x0, in hws_ddr3_tip_init_controller()
624 DRAM_PHY_CFG_REG, data_read, 0x30)); in hws_ddr3_tip_init_controller()
1172 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1176 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1456 DRAM_PHY_CFG_REG, 0, in ddr3_tip_freq_set()
1461 DRAM_PHY_CFG_REG, (0x80000000 | 0x40000000), in ddr3_tip_freq_set()

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