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Searched refs:ESW_SYS_DIV_TRIGGER_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-eth.c31 #define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 macro
86 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()
94 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()
/u-boot/arch/arm/cpu/armv7/bcm281xx/
A Dclk-eth.c31 #define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 macro
86 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()
94 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()

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