| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7629.c | 68 #define FACTOR1(_id, _parent, _mult, _div) \ macro
99 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
100 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4),
101 FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8),
132 FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
135 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
136 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
140 FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1),
141 FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
142 FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1),
[all …]
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| A D | clk-mt7623.c | 78 #define FACTOR1(_id, _parent, _mult, _div) \ macro
108 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
109 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
149 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
150 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
151 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
161 FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
162 FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
163 FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
184 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
[all …]
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| A D | clk-mt7622.c | 74 #define FACTOR1(_id, _parent, _mult, _div) \ macro
101 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
116 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
117 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
118 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
120 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
121 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
122 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
124 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
128 FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
[all …]
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| A D | clk-mt8512.c | 66 #define FACTOR1(_id, _parent, _mult, _div) \ macro
91 FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
92 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
93 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
94 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
95 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
96 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
97 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
98 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
99 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
[all …]
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| A D | clk-mt8518.c | 58 #define FACTOR1(_id, _parent, _mult, _div) \ macro
101 FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
103 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
104 FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
105 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
106 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
113 FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
114 FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
115 FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
116 FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
[all …]
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| A D | clk-mt8516.c | 56 #define FACTOR1(_id, _parent, _mult, _div) \ macro
69 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
100 FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
101 FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
102 FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
104 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
105 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
106 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
109 FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
110 FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
[all …]
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| /u-boot/drivers/thermal/ |
| A D | imx_thermal.c | 27 #define FACTOR1 15423 macro
94 temp64 = div_s64_rem(temp64, FACTOR1 * n1 - FACTOR2, &rem); in read_cpu_temperature()
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