Home
last modified time | relevance | path

Searched refs:FPGA_SET_REG (Results 1 – 9 of 9) sorted by relevance

/u-boot/board/gdsys/common/
A Dmclink.c41 FPGA_SET_REG(k, mc_control, 0x8000); in mclink_probe()
72 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
75 FPGA_SET_REG(0, mc_tx_address, addr); in mclink_send()
76 FPGA_SET_REG(0, mc_tx_data, data); in mclink_send()
77 FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); in mclink_send()
78 FPGA_SET_REG(0, mc_control, 0x8001); in mclink_send()
106 FPGA_SET_REG(0, mc_tx_address, addr); in mclink_receive()
107 FPGA_SET_REG(0, mc_tx_cmd, in mclink_receive()
109 FPGA_SET_REG(0, mc_control, 0x8001); in mclink_receive()
A Dcmd_ioloop.c88 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
93 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
157 FPGA_SET_REG(fpga, ep.transmit_data, *p++); in io_send()
160 FPGA_SET_REG(fpga, ep.transmit_data, k); in io_send()
162 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_send()
240 FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]); in io_reflect()
242 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_reflect()
287 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); in do_ioreflect()
290 FPGA_SET_REG(fpga, ep.device_address, 1); in do_ioreflect()
405 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); in do_ioloop()
[all …]
A Dosd.c45 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
47 FPGA_SET_REG(screen, osd0.fld, val); \
51 FPGA_SET_REG(screen, osd0.fld, val)
130 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); in mpc92469ac_set()
252 FPGA_SET_REG(screen - OSD_DH_BASE, in osd_write_videomem()
255 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); in osd_write_videomem()
257 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); in osd_write_videomem()
A Dihs_mdio.c66 FPGA_SET_REG(info->fpga, mdio.control, val); in write_control()
75 FPGA_SET_REG(info->fpga, mdio.address_data, val); in write_addr_data()
/u-boot/board/gdsys/mpc8308/
A Dstrider.c298 FPGA_SET_REG(bus, gpio.set, pin); in fpga_gpio_set()
303 FPGA_SET_REG(bus, gpio.clear, pin); in fpga_gpio_clear()
321 FPGA_SET_REG(bus, control, val | pin); in fpga_control_set()
329 FPGA_SET_REG(bus, control, val & ~pin); in fpga_control_clear()
451 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
453 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
462 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
472 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
474 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
498 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); in mii_set_mdc()
[all …]
A Dhrcon.c245 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); in fpga_gpio_set()
250 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); in fpga_gpio_clear()
267 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); in fpga_control_set()
275 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); in fpga_control_clear()
396 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
398 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
407 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
417 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
419 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
443 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); in mii_set_mdc()
[all …]
A Dmpc8308.c105 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); in board_early_init_r()
/u-boot/drivers/i2c/
A Dihs_i2c.c50 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
52 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
56 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
/u-boot/include/
A Dgdsys_fpga.h26 #define FPGA_SET_REG(ix, fld, val) \ macro

Completed in 11 milliseconds