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Searched refs:FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch2_serdes.c56 cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
188 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()
369 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()
417 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK, in fsl_serdes_init()
/u-boot/board/freescale/ls1046aqds/
A Deth.c278 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in board_eth_init()
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dimmap_lsch2.h287 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff macro

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