Searched refs:FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK (Results 1 – 6 of 6) sorted by relevance
384 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 macro388 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK401 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 macro407 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
507 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) in initialize_dpmac_to_slot()661 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) in ls2080a_handle_phy_interface_sgmii()804 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) in ls2080a_handle_phy_interface_qsgmii()869 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) in ls2080a_handle_phy_interface_xsgmii()904 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) in board_eth_init()1063 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_fit_config_name_match()
37 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_eth_init()
55 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_eth_init()
466 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_eth_init()934 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_fit_config_name_match()
487 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_eth_init()951 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; in board_fit_config_name_match()
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