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Searched refs:FSL_SRDSCR1_PLLBW (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc83xx/
A Dserdes.c27 #define FSL_SRDSCR1_PLLBW 0x00000040 macro
84 tmp &= ~FSL_SRDSCR1_PLLBW; in fsl_setup_serdes()
107 tmp |= FSL_SRDSCR1_PLLBW; in fsl_setup_serdes()
129 tmp &= ~FSL_SRDSCR1_PLLBW; in fsl_setup_serdes()

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