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Searched refs:FSL_SRDSCR2_SEIC_SGMII (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc83xx/
A Dserdes.c33 #define FSL_SRDSCR2_SEIC_SGMII 0x00000101 macro
135 tmp |= FSL_SRDSCR2_SEIC_SGMII; in fsl_setup_serdes()

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