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Searched refs:FSL_SRDSCR3_OFFS (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
A Dmpc8536_serdes.c45 #define FSL_SRDSCR3_OFFS 0xc macro
135 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
140 out_be32(sd + FSL_SRDSCR3_OFFS, tmp); in fsl_serdes_init()
159 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
162 out_be32(sd + FSL_SRDSCR3_OFFS, tmp); in fsl_serdes_init()
185 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
190 out_be32(sd + FSL_SRDSCR3_OFFS, tmp); in fsl_serdes_init()
209 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
212 out_be32(sd + FSL_SRDSCR3_OFFS, tmp); in fsl_serdes_init()
/u-boot/arch/powerpc/cpu/mpc83xx/
A Dserdes.c34 #define FSL_SRDSCR3_OFFS 0xc macro
97 out_be32(regs + FSL_SRDSCR3_OFFS, tmp); in fsl_setup_serdes()
118 out_be32(regs + FSL_SRDSCR3_OFFS, tmp); in fsl_setup_serdes()
139 out_be32(regs + FSL_SRDSCR3_OFFS, 0); in fsl_setup_serdes()

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