Home
last modified time | relevance | path

Searched refs:Fld (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/
A DSA-1100.h280 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
322 #define UDCWC_WC Fld (4, 0) /* Write Count */
961 #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
965 #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
1041 #define SSCR0_FRF Fld (2, 4) /* FRame Format */
1934 Fld (16, ((Nb) Modulo 2)*16)
2010 Fld (15, (Nb)*16)
2048 #define MDREFR_TRASR Fld (4, 0)
2049 #define MDREFR_DRI Fld (12, 4)
2443 #define DDAR_DS Fld (4, 4) /* Device Select */
[all …]
/u-boot/arch/arm/include/asm/arch-pxa/
A Dbitfield.h45 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
A Dpxa-regs.h2134 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2138 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2143 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2149 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2156 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2160 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2166 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2172 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2192 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
2197 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
[all …]
/u-boot/arch/arm/include/asm/arch-sa1100/
A Dbitfield.h45 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro

Completed in 27 milliseconds