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/u-boot/lib/
A Dsha256.c62 uint32_t A, B, C, D, E, F, G, H; in sha256_process() local
111 G = ctx->state[6]; in sha256_process()
114 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process()
115 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process()
116 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process()
117 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process()
118 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process()
119 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process()
120 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process()
121 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process()
[all …]
/u-boot/arch/arm/dts/
A Darmada-8040-mcbin.dts92 * [49] 10G port 1 interrupt
94 * [51] 2.5G SFP TX fault
96 * [53] 2.5G SFP mode
97 * [54] 2.5G SFP LOS
170 * Lane 4: SFI (10G)
221 * [8] CP1 10G SFP LOS
222 * [9] CP1 10G PHY RESET
224 * [11] CP1 10G SFP Mode
232 * [27] CP0 10G SFP Mode
233 * [28] CP0 10G SFP LOS
[all …]
A Darmada-8040-puzzle-m801.dts102 * [49] 10G port 1 interrupt
104 * [51] 2.5G SFP TX fault
106 * [53] 2.5G SFP mode
107 * [54] 2.5G SFP LOS
219 * Lane 4: SFI (10G)
296 * [8] CP1 10G SFP LOS
297 * [9] CP1 10G PHY RESET
299 * [11] CP1 10G SFP Mode
307 * [27] CP0 10G SFP Mode
308 * [28] CP0 10G SFP LOS
[all …]
A Dstm32mp15-pinctrl.dtsi374 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
403 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
567 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
568 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
603 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
604 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
755 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
770 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
772 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
773 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
[all …]
A Dstm32746g-eval-u-boot.dtsi73 <STM32_PINMUX('G',13, AF11)>, /*ETH_MII_TXD0 */
74 <STM32_PINMUX('G',14, AF11)>, /*ETH_MII_TXD1 */
82 <STM32_PINMUX('G',11, AF11)>, /*ETH_MII_TX_EN */
130 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
131 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
133 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
134 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
149 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
151 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32f746-disco-u-boot.dtsi108 pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
109 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
110 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
143 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
144 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
146 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
147 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
162 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
164 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
172 <STM32_PINMUX('G',12, AF14)>, /* B4 */
A Darmada-xp-crs305-1g-4s.dts3 * Device Tree file for MikroTik CRS305-1G-4S+ board
12 model = "MikroTik CRS305-1G-4S+";
A Darmada-xp-crs326-24g-2s.dts3 * Device Tree file for MikroTik CRS326-24G-2S+ board
12 model = "MikroTik CRS326-24G-2S+";
A Dstm32f769-disco-u-boot.dtsi126 pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
127 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
128 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
180 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
181 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
183 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
184 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
199 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
201 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32429i-eval-u-boot.dtsi192 <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
193 <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */
194 <STM32_PINMUX('G', 3, AF12)>, /* A13 */
195 <STM32_PINMUX('G', 2, AF12)>, /* A12 */
196 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
197 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
212 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
214 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32h7-u-boot.dtsi174 <STM32_PINMUX('G', 0, AF12)>,
175 <STM32_PINMUX('G', 1, AF12)>,
176 <STM32_PINMUX('G', 2, AF12)>,
177 <STM32_PINMUX('G', 4, AF12)>,
178 <STM32_PINMUX('G', 5, AF12)>,
179 <STM32_PINMUX('G', 8, AF12)>,
180 <STM32_PINMUX('G',15, AF12)>,
A Dstm32f429-disco-u-boot.dtsi160 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
161 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
163 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
164 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
179 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
181 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
A Darmada-xp-crs305-1g-4s-bit.dts3 * Device Tree file for MikroTik CRS305-1G-4S+ Bit board
12 model = "MikroTik CRS305-1G-4S+ Bit";
A Darmada-xp-crs326-24g-2s-bit.dts3 * Device Tree file for MikroTik CRS326-24G-2S+ Bit board
12 model = "MikroTik CRS326-24G-2S+ Bit";
A Dstm32f469-disco-u-boot.dtsi184 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
185 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
187 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
188 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
203 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
205 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32f4-pinctrl.dtsi200 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
201 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
205 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
289 <STM32_PINMUX('G', 7, AF14)>,
301 <STM32_PINMUX('G', 6, AF14)>,
305 <STM32_PINMUX('G', 10, AF9)>,
311 <STM32_PINMUX('G', 11, AF14)>,
319 <STM32_PINMUX('G', 12, AF9)>,
/u-boot/doc/
A DREADME.mpc85xx57 Properties : 1M, AS1, I, G, IPROT
69 Properties : 1M, AS1, I, G
88 Properties : Board specific size, AS0, I, G, IPROT
98 Properties : 1M, AS1, I, G, IPROT
101 Properties : 4M, AS0, I, G, IPROT
109 Properties : 1M, AS1, I, G, IPROT
112 Properties : 4M, AS1, I, G, IPROT
125 Properties : 1M, AS1, I, G
137 Properties : 4M, AS1, I, G, IPROT
143 Properties : 4M, AS0, I, G, IPROT
[all …]
/u-boot/arch/x86/include/asm/arch-quark/acpi/
A Dirqroute.h9 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
10 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
/u-boot/scripts/kconfig/tests/err_recursive_dep/
A DKconfig58 depends on G
60 config G config
61 bool "G"
/u-boot/include/
A Dsignatures.h59 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ argument
60 (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
/u-boot/board/freescale/t208xrdb/
A DREADME45 1G Ethernet numbers: 8 6
46 10G Ethernet numbers: 4 2
57 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
58 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
62 - SerDes-2 Lane G-H: to SATA1 & SATA2
64 - Two on-board 10M/100M/1G RGMII ethernet ports
136 ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
137 ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
138 ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
139 ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
[all …]
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.soc34 - Up to 1 x XFI supporting 10G interface
191 - Support for 10G operation
262 c) 5 * 1/10G + 5 *1G WRIOP
296 Support for 10G-SXGMII (aka USXGMII).
299 Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
300 Support for XLAUI (and 40GBase-KR4) for 40G.
356 - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
357 ethernet MAC supporting 1G, 100M, 10M.
361 - Support for 10G-SXGMII and 10G-QXGMII.
401 Support for 10G-SXGMII (aka USXGMII).
[all …]
/u-boot/board/freescale/lx2160a/
A DREADME116 13 |Mezzanine:X-M8-100G (29734)
119 |Mezzanine:X-M8-100G (29734)
123 15 |Mezzanine:X-M8-100G (29734)
130 17 |Mezzanine:X-M13-25G (32133)
137 19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
140 |Mezzanine:X-M7-40G (29738)
144 20 |Mezzanine:X-M7-40G (29738)
147 |Mezzanine:X-M7-40G (29738)
284 15 |Mezzanine:X-M8-50G (29734)
288 17 |Mezzanine:X-M13-25G (32133)
[all …]
/u-boot/board/congatec/
A DKconfig17 (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM.
29 conga-QA3/E3845-4G SoM. It contains an Atom E3845 with Ethernet,
/u-boot/board/freescale/ls1046afrwy/
A DREADME54 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
55 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
56 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G

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