1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
6 */
7
8 #define LOG_CATEGORY UCLASS_VIDEO
9
10 #include <common.h>
11 #include <clk.h>
12 #include <display.h>
13 #include <dm.h>
14 #include <log.h>
15 #include <panel.h>
16 #include <reset.h>
17 #include <video.h>
18 #include <video_bridge.h>
19 #include <asm/io.h>
20 #include <asm/arch/gpio.h>
21 #include <dm/device-internal.h>
22 #include <dm/device_compat.h>
23 #include <linux/bitops.h>
24
25 struct stm32_ltdc_priv {
26 void __iomem *regs;
27 enum video_log2_bpp l2bpp;
28 u32 bg_col_argb;
29 u32 crop_x, crop_y, crop_w, crop_h;
30 u32 alpha;
31 };
32
33 /* LTDC main registers */
34 #define LTDC_IDR 0x00 /* IDentification */
35 #define LTDC_LCR 0x04 /* Layer Count */
36 #define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
37 #define LTDC_BPCR 0x0C /* Back Porch Configuration */
38 #define LTDC_AWCR 0x10 /* Active Width Configuration */
39 #define LTDC_TWCR 0x14 /* Total Width Configuration */
40 #define LTDC_GCR 0x18 /* Global Control */
41 #define LTDC_GC1R 0x1C /* Global Configuration 1 */
42 #define LTDC_GC2R 0x20 /* Global Configuration 2 */
43 #define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
44 #define LTDC_GACR 0x28 /* GAmma Correction */
45 #define LTDC_BCCR 0x2C /* Background Color Configuration */
46 #define LTDC_IER 0x34 /* Interrupt Enable */
47 #define LTDC_ISR 0x38 /* Interrupt Status */
48 #define LTDC_ICR 0x3C /* Interrupt Clear */
49 #define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
50 #define LTDC_CPSR 0x44 /* Current Position Status */
51 #define LTDC_CDSR 0x48 /* Current Display Status */
52
53 /* LTDC layer 1 registers */
54 #define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
55 #define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
56 #define LTDC_L1CR 0x84 /* L1 Control */
57 #define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
58 #define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
59 #define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
60 #define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
61 #define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
62 #define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
63 #define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
64 #define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
65 #define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
66 #define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
67 #define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
68 #define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
69 #define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
70 #define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
71 #define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
72 #define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
73
74 /* Bit definitions */
75 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
76 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
77
78 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
79 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
80
81 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
82 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
83
84 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
85 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
86
87 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
88 #define GCR_DEN BIT(16) /* Dither ENable */
89 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
90 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
91 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
92 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
93
94 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
95 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
96 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
97 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
98 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
99 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
100 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
101 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
102 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
103 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
104 #define GC1R_TP BIT(25) /* Timing Programmable */
105 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
106 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
107 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
108 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
109 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
110
111 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
112 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
113 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
114 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
115 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
116 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
117
118 #define SRCR_IMR BIT(0) /* IMmediate Reload */
119 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
120
121 #define LXCR_LEN BIT(0) /* Layer ENable */
122 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
123 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
124
125 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
126 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
127
128 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
129 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
130
131 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
132
133 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
134
135 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
136 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
137
138 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
139 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
140
141 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
142
143 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
144 #define BF1_CA 0x400 /* Constant Alpha */
145 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
146 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
147
148 enum stm32_ltdc_pix_fmt {
149 PF_ARGB8888 = 0,
150 PF_RGB888,
151 PF_RGB565,
152 PF_ARGB1555,
153 PF_ARGB4444,
154 PF_L8,
155 PF_AL44,
156 PF_AL88
157 };
158
159 /* TODO add more color format support */
stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)160 static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
161 {
162 enum stm32_ltdc_pix_fmt pf;
163
164 switch (l2bpp) {
165 case VIDEO_BPP16:
166 pf = PF_RGB565;
167 break;
168
169 case VIDEO_BPP32:
170 pf = PF_ARGB8888;
171 break;
172
173 case VIDEO_BPP8:
174 pf = PF_L8;
175 break;
176
177 case VIDEO_BPP1:
178 case VIDEO_BPP2:
179 case VIDEO_BPP4:
180 default:
181 log_warning("warning %dbpp not supported yet, %dbpp instead\n",
182 VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
183 pf = PF_RGB565;
184 break;
185 }
186
187 log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
188
189 return (u32)pf;
190 }
191
has_alpha(u32 fmt)192 static bool has_alpha(u32 fmt)
193 {
194 switch (fmt) {
195 case PF_ARGB8888:
196 case PF_ARGB1555:
197 case PF_ARGB4444:
198 case PF_AL44:
199 case PF_AL88:
200 return true;
201 case PF_RGB888:
202 case PF_RGB565:
203 case PF_L8:
204 default:
205 return false;
206 }
207 }
208
stm32_ltdc_enable(struct stm32_ltdc_priv * priv)209 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
210 {
211 /* Reload configuration immediately & enable LTDC */
212 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
213 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
214 }
215
stm32_ltdc_set_mode(struct stm32_ltdc_priv * priv,struct display_timing * timings)216 static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
217 struct display_timing *timings)
218 {
219 void __iomem *regs = priv->regs;
220 u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
221 u32 total_w, total_h;
222 u32 val;
223
224 /* Convert video timings to ltdc timings */
225 hsync = timings->hsync_len.typ - 1;
226 vsync = timings->vsync_len.typ - 1;
227 acc_hbp = hsync + timings->hback_porch.typ;
228 acc_vbp = vsync + timings->vback_porch.typ;
229 acc_act_w = acc_hbp + timings->hactive.typ;
230 acc_act_h = acc_vbp + timings->vactive.typ;
231 total_w = acc_act_w + timings->hfront_porch.typ;
232 total_h = acc_act_h + timings->vfront_porch.typ;
233
234 /* Synchronization sizes */
235 val = (hsync << 16) | vsync;
236 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
237
238 /* Accumulated back porch */
239 val = (acc_hbp << 16) | acc_vbp;
240 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
241
242 /* Accumulated active width */
243 val = (acc_act_w << 16) | acc_act_h;
244 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
245
246 /* Total width & height */
247 val = (total_w << 16) | total_h;
248 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
249
250 setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
251
252 /* Signal polarities */
253 val = 0;
254 log_debug("timing->flags 0x%08x\n", timings->flags);
255 if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
256 val |= GCR_HSPOL;
257 if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
258 val |= GCR_VSPOL;
259 if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
260 val |= GCR_DEPOL;
261 if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
262 val |= GCR_PCPOL;
263 clrsetbits_le32(regs + LTDC_GCR,
264 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
265
266 /* Overall background color */
267 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
268 }
269
stm32_ltdc_set_layer1(struct stm32_ltdc_priv * priv,ulong fb_addr)270 static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
271 {
272 void __iomem *regs = priv->regs;
273 u32 x0, x1, y0, y1;
274 u32 pitch_in_bytes;
275 u32 line_length;
276 u32 bus_width;
277 u32 val, tmp, bpp;
278 u32 format;
279
280 x0 = priv->crop_x;
281 x1 = priv->crop_x + priv->crop_w - 1;
282 y0 = priv->crop_y;
283 y1 = priv->crop_y + priv->crop_h - 1;
284
285 /* Horizontal start and stop position */
286 tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
287 val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
288 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
289 val);
290
291 /* Vertical start & stop position */
292 tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
293 val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
294 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
295 val);
296
297 /* Layer background color */
298 writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
299
300 /* Color frame buffer pitch in bytes & line length */
301 bpp = VNBITS(priv->l2bpp);
302 pitch_in_bytes = priv->crop_w * (bpp >> 3);
303 bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
304 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
305 val = (pitch_in_bytes << 16) | line_length;
306 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
307
308 /* Pixel format */
309 format = stm32_ltdc_get_pixel_format(priv->l2bpp);
310 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
311
312 /* Constant alpha value */
313 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
314
315 /* Specifies the blending factors : with or without pixel alpha */
316 /* Manage hw-specific capabilities */
317 val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
318
319 /* Blending factors */
320 clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
321
322 /* Frame buffer line number */
323 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
324
325 /* Frame buffer address */
326 writel(fb_addr, regs + LTDC_L1CFBAR);
327
328 /* Enable layer 1 */
329 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
330 }
331
stm32_ltdc_probe(struct udevice * dev)332 static int stm32_ltdc_probe(struct udevice *dev)
333 {
334 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
335 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
336 struct stm32_ltdc_priv *priv = dev_get_priv(dev);
337 struct udevice *bridge = NULL;
338 struct udevice *panel = NULL;
339 struct display_timing timings;
340 struct clk pclk;
341 struct reset_ctl rst;
342 int ret;
343
344 priv->regs = (void *)dev_read_addr(dev);
345 if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
346 dev_err(dev, "ltdc dt register address error\n");
347 return -EINVAL;
348 }
349
350 ret = clk_get_by_index(dev, 0, &pclk);
351 if (ret) {
352 dev_err(dev, "peripheral clock get error %d\n", ret);
353 return ret;
354 }
355
356 ret = clk_enable(&pclk);
357 if (ret) {
358 dev_err(dev, "peripheral clock enable error %d\n", ret);
359 return ret;
360 }
361
362 ret = uclass_first_device_err(UCLASS_PANEL, &panel);
363 if (ret) {
364 if (ret != -ENODEV)
365 dev_err(dev, "panel device error %d\n", ret);
366 return ret;
367 }
368
369 ret = panel_get_display_timing(panel, &timings);
370 if (ret) {
371 ret = ofnode_decode_display_timing(dev_ofnode(panel),
372 0, &timings);
373 if (ret) {
374 dev_err(dev, "decode display timing error %d\n", ret);
375 return ret;
376 }
377 }
378
379 ret = clk_set_rate(&pclk, timings.pixelclock.typ);
380 if (ret)
381 dev_warn(dev, "fail to set pixel clock %d hz\n",
382 timings.pixelclock.typ);
383
384 dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
385 timings.pixelclock.typ, clk_get_rate(&pclk));
386
387 ret = reset_get_by_index(dev, 0, &rst);
388 if (ret) {
389 dev_err(dev, "missing ltdc hardware reset\n");
390 return ret;
391 }
392
393 /* Reset */
394 reset_deassert(&rst);
395
396 if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
397 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
398 if (ret)
399 dev_dbg(dev,
400 "No video bridge, or no backlight on bridge\n");
401
402 if (bridge) {
403 ret = video_bridge_attach(bridge);
404 if (ret) {
405 dev_err(bridge, "fail to attach bridge\n");
406 return ret;
407 }
408 }
409 }
410
411 /* TODO Below parameters are hard-coded for the moment... */
412 priv->l2bpp = VIDEO_BPP16;
413 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
414 priv->crop_x = 0;
415 priv->crop_y = 0;
416 priv->crop_w = timings.hactive.typ;
417 priv->crop_h = timings.vactive.typ;
418 priv->alpha = 0xFF;
419
420 dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
421 timings.hactive.typ, timings.vactive.typ,
422 VNBITS(priv->l2bpp), uc_plat->base);
423 dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
424 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
425 priv->bg_col_argb, priv->alpha);
426
427 /* Configure & start LTDC */
428 stm32_ltdc_set_mode(priv, &timings);
429 stm32_ltdc_set_layer1(priv, uc_plat->base);
430 stm32_ltdc_enable(priv);
431
432 uc_priv->xsize = timings.hactive.typ;
433 uc_priv->ysize = timings.vactive.typ;
434 uc_priv->bpix = priv->l2bpp;
435
436 if (!bridge) {
437 ret = panel_enable_backlight(panel);
438 if (ret) {
439 dev_err(dev, "panel %s enable backlight error %d\n",
440 panel->name, ret);
441 return ret;
442 }
443 } else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
444 ret = video_bridge_set_backlight(bridge, 80);
445 if (ret) {
446 dev_err(dev, "fail to set backlight\n");
447 return ret;
448 }
449 }
450
451 video_set_flush_dcache(dev, true);
452
453 return 0;
454 }
455
stm32_ltdc_bind(struct udevice * dev)456 static int stm32_ltdc_bind(struct udevice *dev)
457 {
458 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
459
460 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
461 CONFIG_VIDEO_STM32_MAX_YRES *
462 (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
463 dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size);
464
465 return 0;
466 }
467
468 static const struct udevice_id stm32_ltdc_ids[] = {
469 { .compatible = "st,stm32-ltdc" },
470 { }
471 };
472
473 U_BOOT_DRIVER(stm32_ltdc) = {
474 .name = "stm32_display",
475 .id = UCLASS_VIDEO,
476 .of_match = stm32_ltdc_ids,
477 .probe = stm32_ltdc_probe,
478 .bind = stm32_ltdc_bind,
479 .priv_auto = sizeof(struct stm32_ltdc_priv),
480 };
481