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Searched refs:GMAC0_DMA_RX_CTRL_ADDR (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/net/
A Dbcm-sf2-eth-gmac.h40 #define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220) macro
42 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
44 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
46 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
48 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
50 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
A Dbcm-sf2-eth-gmac.c139 readl(GMAC0_DMA_RX_CTRL_ADDR), in dma_rx_dump()
279 (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK) in dma_init()
459 control = readl(GMAC0_DMA_RX_CTRL_ADDR); in gmac_check_rx_done()
518 writel(0, GMAC0_DMA_RX_CTRL_ADDR); in gmac_disable_dma()
559 control = (readl(GMAC0_DMA_RX_CTRL_ADDR) & in gmac_enable_dma()
576 control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK; in gmac_enable_dma()
579 writel(control, GMAC0_DMA_RX_CTRL_ADDR); in gmac_enable_dma()

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