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/u-boot/drivers/gpio/
A DKconfig2 # GPIO infrastructure and drivers
5 menu "GPIO Support"
11 Enable driver model for GPIO access. The standard GPIO
22 Enable driver model for GPIO access in SPL. The standard GPIO
33 Enable driver model for GPIO access in TPL. The standard GPIO
45 The GPIO chip may contain GPIO hog definitions. GPIO hogging
77 bool "BCM6345 GPIO driver"
92 bool "DWAPB GPIO driver"
122 bool "DA8xx GPIO Driver"
330 bool "UniPhier GPIO"
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/u-boot/arch/x86/include/asm/arch-apollolake/acpi/
A Dgpiolib.asl11 /* Arg0 - GPIO DW0 address */
23 /* Arg0 - GPIO DW0 address */
36 /* Arg0 - GPIO DW0 address */
48 /* Arg0 - GPIO DW0 address */
61 /* Arg0 - GPIO portid */
62 /* Arg1 - GPIO pad offset relative to the community */
74 /* Arg0 - GPIO pad offset relative to the community */
79 /* Get Host ownership register of GPIO Community */
82 /* Arg0 - GPIO portid */
94 /* Set Host ownership register of GPIO Community */
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/u-boot/drivers/pinctrl/
A Dpinctrl-kendryte.c196 DEFAULT(GPIO),
246 FUNC(GPIOHS0, GPIO),
247 FUNC(GPIOHS1, GPIO),
248 FUNC(GPIOHS2, GPIO),
249 FUNC(GPIOHS3, GPIO),
250 FUNC(GPIOHS4, GPIO),
251 FUNC(GPIOHS5, GPIO),
252 FUNC(GPIOHS6, GPIO),
253 FUNC(GPIOHS7, GPIO),
254 FUNC(GPIOHS8, GPIO),
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/u-boot/doc/device-tree-bindings/gpio/
A Dgpio.txt1 Specifying GPIO information for devices
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
83 1.1) GPIO specifier best practices
124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
185 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
189 Each GPIO hog definition is represented as a child node of the GPIO controller.
192 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
243 The GPIO controller offset pertains to the GPIO controller node containing the
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A Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
75 - "gpio": Mandatory. GPIO control registers. This may cover either:
96 Marks the device node as a GPIO controller/provider.
100 Indicates how many cells are used in a consumer's GPIO specifier.
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A Dmscc_sgpio.txt1 Microsemi Corporation (MSCC) Serial GPIO driver
3 The MSCC serial GPIO extends the number or GPIO's on the system by
6 effective GPIO count can be extended by up to 128 GPIO's per
17 - gpio-controller : Marks the device node as a GPIO controller.
31 regular GPIO pins.
A Dsnps,creg-gpio.txt1 GPIO via CREG (control registers) driver
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - gpio-count: Number of GPIO pins.
18 - gpio-first-shift: Shift (in bits) of the first GPIO field in register
21 output to "1" (see picture). Applied to all GPIO ports.
23 output to "0" (see picture). Applied to all GPIO ports.
A Dgpio-msm.txt1 Qualcomm Snapdragon GPIO controller
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - gpio-count: Number of GPIO pins.
A Dintel,apl-gpio.txt1 Intel Apollo Lake GPIO controller
3 The Apollo Lake (APL) GPIO controller is used to control GPIO functions of
15 - Pin number: is a GPIO pin number between 0 and 244
A Daltera_pio.txt1 Altera GPIO controller bindings
9 - altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the
10 GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
/u-boot/arch/arm/dts/
A Dhi3798cv200-poplar.dts116 gpio-line-names = "GPIO-E", "",
118 "", "GPIO-F",
119 "", "GPIO-J";
124 gpio-line-names = "GPIO-H", "GPIO-I",
125 "GPIO-L", "GPIO-G",
126 "GPIO-K", "",
134 "GPIO-C", "",
135 "", "GPIO-B";
142 "", "GPIO-D",
150 "", "GPIO-A",
A Dsocfpga_cyclone5_mcvevk.dts35 &gpio0 { /* GPIO 0 ... 28 */
39 &gpio1 { /* GPIO 29 ... 57 */
43 &gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
58 irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
A Dhi3660-hikey960.dts79 label = "GPIO Power";
202 * Legend: proper name = the GPIO line is used as GPIO
224 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
225 * ones actually used for GPIO.
256 "GPIO-J", /* LSEC pin 32: GPIO_019 */
258 "GPIO-L", /* LSEC pin 34: GPIO_021 */
260 "GPIO-G"; /* LSEC pin 29: LCD_TE0 */
265 /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
491 "GPIO-A", /* LSEC pin 23: GPIO_208 */
492 "GPIO-B", /* LSEC pin 24: GPIO_209 */
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A Dexynos54xx-pinctrl-uboot.dtsi3 * U-Boot additions to enable a generic Exynos GPIO driver
11 * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO
/u-boot/board/firefly/roc-pc-rk3399/
A Droc-pc-rk3399.c65 spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); in led_setup()
67 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), in led_setup()
72 spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); in led_setup()
75 spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); in led_setup()
/u-boot/arch/x86/include/asm/
A Dintel_pinctrl_defs.h223 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
231 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
236 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
243 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
250 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
261 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
268 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
275 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
296 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
303 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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/u-boot/doc/device-tree-bindings/spi/
A Dsoft-spi.txt3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
20 The GPIOs should be specified as required by the GPIO controller referenced.
22 typically holds the GPIO number.
/u-boot/doc/device-tree-bindings/pinctrl/
A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
141 GPIO subnode:
144 and the common GPIO bindings used by client devices.
146 Required properties for the GPIO driver under the gpio subnode:
148 - gpio-controller: Marks the device node as a GPIO controller.
150 second cell specifies GPIO flags, as defined in
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A Dst,stm32-pinctrl.txt1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
25 GPIO controller/bank node:
27 - gpio-controller : Indicates this device is a GPIO controller
145 * 0 : GPIO
158 /* GPIO A9 set as alernate function 2 */
162 /* GPIO A9 set as GPIO */
164 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
166 /* GPIO A9 set as analog */
/u-boot/arch/powerpc/cpu/mpc83xx/sysio/
A DKconfig.mpc830875 bool "GPIO"
89 bool "GPIO"
103 bool "GPIO"
108 prompt "GPIO A group"
111 bool "GPIO"
119 prompt "GPIO B group"
122 bool "GPIO"
139 bool "GPIO"
158 bool "GPIO"
166 bool "GPIO"
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/u-boot/arch/x86/include/asm/arch-tangier/acpi/
A Dsouthcluster.asl33 /* GPIO Low Memory Region */
105 GPIO
122 If (^^GPIO.AVBL == One)
124 ^^GPIO.WFD3 = One
136 GPIO
151 If (^^^GPIO.AVBL == One)
153 ^^^GPIO.WFD3 = Zero
162 If (^^^GPIO.AVBL == One)
164 ^^^GPIO.WFD3 = One
295 Device (GPIO)
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/u-boot/drivers/pinctrl/renesas/
A DKconfig17 the GPIO definitions and pin control functions for each available
27 the GPIO definitions and pin control functions for each available
37 the GPIO definitions and pin control functions for each available
47 the GPIO definitions and pin control functions for each available
57 the GPIO definitions and pin control functions for each available
97 the GPIO definitions and pin control functions for each available
107 the GPIO definitions and pin control functions for each available
117 the GPIO definitions and pin control functions for each available
127 the GPIO definitions and pin control functions for each available
137 the GPIO definitions and pin control functions for each available
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/u-boot/board/intel/cherryhill/
A Dcherryhill.c29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
50 GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
53 GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
56 GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
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/u-boot/doc/device-tree-bindings/video/
A Dtegra20-dc.txt33 Optional GPIO properies all have (phandle, GPIO number, flags):
34 - nvidia,backlight-enable-gpios: backlight enable GPIO
35 - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO
36 - nvidia,backlight-vdd-gpios: backlight power GPIO
37 - nvidia,panel-vdd-gpios: panel power GPIO
/u-boot/drivers/i2c/muxes/
A DKconfig20 bool "GPIO-based I2C arbitration"
26 a GPIO.
40 tristate "GPIO-based I2C multiplexer"
44 a GPIO based I2C multiplexer. This driver provides access to
46 through GPIO pins.

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