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Searched refs:HHI_HDMI_PLL_CNTL (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/video/meson/
A Dmeson_vclk.c221 hhi_write(HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
242 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
244 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
447 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
463 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
465 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
500 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
505 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
525 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
536 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
[all …]
/u-boot/arch/arm/include/asm/arch-meson/
A Dclock-gx.h97 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro

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