HIT_WRITEBACK_INV_D (reference) in projects: u-boot

Searched refs:HIT_WRITEBACK_INV_D (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/mips/lib/
A D	cache.c	`124 HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); in flush_cache() 129 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); in flush_cache() 154 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); in flush_dcache_range()`
/u-boot/arch/mips/include/asm/
A D	cacheops.h	`60 #define HIT_WRITEBACK_INV_D 0x15 macro`
/u-boot/arch/mips/mach-mtmips/mt7628/
A D	lowlevel_init.S	`146 cache HIT_WRITEBACK_INV_D, 0(a0)`

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