1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk>
4 *
5 * Based on the Linux driver, (C) 2012 Texas Instruments
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <display.h>
11 #include <i2c.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14
15 /*
16 * TDA19988 uses paged registers. We encode the page# in the upper
17 * bits of the register#. It also means that reads/writes to a register
18 * have to ensure that the register's page is selected as the current
19 * page.
20 */
21 #define REG(page, addr) (((page) << 8) | (addr))
22 #define REG2ADDR(reg) ((reg) & 0xff)
23 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
24
25 /* register for setting current page */
26 #define REG_CURRENT_PAGE 0xff
27
28 /* Page 00h: General Control */
29 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
30 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
31 #define MAIN_CNTRL0_SR BIT(0)
32 #define MAIN_CNTRL0_DECS BIT(1)
33 #define MAIN_CNTRL0_DEHS BIT(2)
34 #define MAIN_CNTRL0_CECS BIT(3)
35 #define MAIN_CNTRL0_CEHS BIT(4)
36 #define MAIN_CNTRL0_SCALER BIT(7)
37 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
38 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
39 #define SOFTRESET_AUDIO BIT(0)
40 #define SOFTRESET_I2C_MASTER BIT(1)
41 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
42 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
43 #define I2C_MASTER_DIS_MM BIT(0)
44 #define I2C_MASTER_DIS_FILT BIT(1)
45 #define I2C_MASTER_APP_STRT_LAT BIT(2)
46 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
47 #define FEAT_POWERDOWN_PREFILT BIT(0)
48 #define FEAT_POWERDOWN_CSC BIT(1)
49 #define FEAT_POWERDOWN_SPDIF BIT(3)
50 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
51 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
52 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
53 #define INT_FLAGS_2_EDID_BLK_RD BIT(1)
54 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
55 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
56 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
57 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
58 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
59 #define VIP_CNTRL_0_MIRR_A BIT(7)
60 #define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
61 #define VIP_CNTRL_0_MIRR_B BIT(3)
62 #define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
63 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
64 #define VIP_CNTRL_1_MIRR_C BIT(7)
65 #define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
66 #define VIP_CNTRL_1_MIRR_D BIT(3)
67 #define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
68 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
69 #define VIP_CNTRL_2_MIRR_E BIT(7)
70 #define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
71 #define VIP_CNTRL_2_MIRR_F BIT(3)
72 #define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
73 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
74 #define VIP_CNTRL_3_X_TGL BIT(0)
75 #define VIP_CNTRL_3_H_TGL BIT(1)
76 #define VIP_CNTRL_3_V_TGL BIT(2)
77 #define VIP_CNTRL_3_EMB BIT(3)
78 #define VIP_CNTRL_3_SYNC_DE BIT(4)
79 #define VIP_CNTRL_3_SYNC_HS BIT(5)
80 #define VIP_CNTRL_3_DE_INT BIT(6)
81 #define VIP_CNTRL_3_EDGE BIT(7)
82 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
83 #define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
84 #define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
85 #define VIP_CNTRL_4_CCIR656 BIT(4)
86 #define VIP_CNTRL_4_656_ALT BIT(5)
87 #define VIP_CNTRL_4_TST_656 BIT(6)
88 #define VIP_CNTRL_4_TST_PAT BIT(7)
89 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
90 #define VIP_CNTRL_5_CKCASE BIT(0)
91 #define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
92 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
93 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
94 #define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
95 #define MAT_CONTRL_MAT_BP BIT(2)
96 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
97 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
98 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
99 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
100 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
101 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
102 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
103 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
104 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
105 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
106 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
107 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
108 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
109 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
110 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
111 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
112 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
113 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
114 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
115 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
116 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
117 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
118 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
119 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
120 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
121 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
122 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
123 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
124 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
125 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
126 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
127 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
128 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
129 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
130 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
131 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
132 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
133 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
134 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
135 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
136 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
137 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
138 #define TBG_CNTRL_0_TOP_TGL BIT(0)
139 #define TBG_CNTRL_0_TOP_SEL BIT(1)
140 #define TBG_CNTRL_0_DE_EXT BIT(2)
141 #define TBG_CNTRL_0_TOP_EXT BIT(3)
142 #define TBG_CNTRL_0_FRAME_DIS BIT(5)
143 #define TBG_CNTRL_0_SYNC_MTHD BIT(6)
144 #define TBG_CNTRL_0_SYNC_ONCE BIT(7)
145 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
146 #define TBG_CNTRL_1_H_TGL BIT(0)
147 #define TBG_CNTRL_1_V_TGL BIT(1)
148 #define TBG_CNTRL_1_TGL_EN BIT(2)
149 #define TBG_CNTRL_1_X_EXT BIT(3)
150 #define TBG_CNTRL_1_H_EXT BIT(4)
151 #define TBG_CNTRL_1_V_EXT BIT(5)
152 #define TBG_CNTRL_1_DWIN_DIS BIT(6)
153 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
154 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
155 #define HVF_CNTRL_0_SM BIT(7)
156 #define HVF_CNTRL_0_RWB BIT(6)
157 #define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
158 #define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
159 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
160 #define HVF_CNTRL_1_FOR BIT(0)
161 #define HVF_CNTRL_1_YUVBLK BIT(1)
162 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
163 #define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
164 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
165 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
166 #define AIP_CLKSEL_AIP_SPDIF (0 << 3)
167 #define AIP_CLKSEL_AIP_I2S BIT(3)
168 #define AIP_CLKSEL_FS_ACLK (0 << 0)
169 #define AIP_CLKSEL_FS_MCLK BIT(0)
170
171 /* Page 02h: PLL settings */
172 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
173 #define PLL_SERIAL_1_SRL_FDN BIT(0)
174 #define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
175 #define PLL_SERIAL_1_SRL_MAN_IZ BIT(6)
176 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
177 #define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
178 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
179 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
180 #define PLL_SERIAL_3_SRL_CCIR BIT(0)
181 #define PLL_SERIAL_3_SRL_DE BIT(2)
182 #define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4)
183 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
184 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
185 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
186 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
187 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
188 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
189 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
190 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
191 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
192 #define AUDIO_DIV_SERCLK_1 0
193 #define AUDIO_DIV_SERCLK_2 1
194 #define AUDIO_DIV_SERCLK_4 2
195 #define AUDIO_DIV_SERCLK_8 3
196 #define AUDIO_DIV_SERCLK_16 4
197 #define AUDIO_DIV_SERCLK_32 5
198 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
199 #define SEL_CLK_SEL_CLK1 BIT(0)
200 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
201 #define SEL_CLK_ENA_SC_CLK BIT(3)
202 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
203
204 /* Page 09h: EDID Control */
205 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
206 /* next 127 successive registers are the EDID block */
207 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
208 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
209 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
210 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
211 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
212
213 /* Page 11h: audio settings and content info packets */
214 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
215 #define AIP_CNTRL_0_RST_FIFO BIT(0)
216 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
217 #define ENC_CNTRL_RST_ENC BIT(0)
218 #define ENC_CNTRL_RST_SEL BIT(1)
219 #define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
220
221 /* Page 12h: HDCP and OTP */
222 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
223 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
224 #define TX4_PD_RAM BIT(1)
225 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
226 #define TX33_HDMI BIT(1)
227
228 /* CEC registers, not paged */
229 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
230 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7)
231 #define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6)
232 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1)
233 #define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0)
234 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
235 #define REG_CEC_RXSHPDINT 0xfd /* read */
236 #define CEC_RXSHPDINT_RXSENS BIT(0)
237 #define CEC_RXSHPDINT_HPD BIT(1)
238 #define TDA19988_CEC_ENAMODS 0xff /* read/write */
239 #define CEC_ENAMODS_EN_RXSENS BIT(2)
240 #define CEC_ENAMODS_EN_HDMI BIT(1)
241 #define CEC_ENAMODS_EN_CEC BIT(0)
242
243 /* Device versions */
244 #define TDA9989N2 0x0101
245 #define TDA19989 0x0201
246 #define TDA19989N2 0x0202
247 #define TDA19988 0x0301
248
249 struct tda19988_priv {
250 struct udevice *chip;
251 struct udevice *cec_chip;
252 u16 revision;
253 u8 current_page;
254 };
255
tda19988_register_set(struct tda19988_priv * priv,u16 reg,u8 val)256 static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val)
257 {
258 u8 old_val, page = REG2PAGE(reg);
259
260 if (priv->current_page != page) {
261 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
262 priv->current_page = page;
263 }
264 old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
265 old_val |= val;
266 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
267 }
268
tda19988_register_clear(struct tda19988_priv * priv,u16 reg,u8 val)269 static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val)
270 {
271 u8 old_val, page = REG2PAGE(reg);
272
273 if (priv->current_page != page) {
274 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
275 priv->current_page = page;
276 }
277 old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
278 old_val &= ~val;
279 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
280 }
281
tda19988_register_write(struct tda19988_priv * priv,u16 reg,u8 val)282 static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val)
283 {
284 u8 page = REG2PAGE(reg);
285
286 if (priv->current_page != page) {
287 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
288 priv->current_page = page;
289 }
290 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val);
291 }
292
tda19988_register_read(struct tda19988_priv * priv,u16 reg)293 static int tda19988_register_read(struct tda19988_priv *priv, u16 reg)
294 {
295 u8 page = REG2PAGE(reg);
296
297 if (priv->current_page != page) {
298 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
299 priv->current_page = page;
300 }
301 return dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
302 }
303
tda19988_register_write16(struct tda19988_priv * priv,u16 reg,u16 val)304 static void tda19988_register_write16(struct tda19988_priv *priv,
305 u16 reg, u16 val)
306 {
307 u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg);
308
309 if (priv->current_page != page) {
310 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
311 priv->current_page = page;
312 }
313 dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2);
314 }
315
tda19988_read_edid(struct udevice * dev,u8 * buf,int buf_size)316 static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size)
317 {
318 struct tda19988_priv *priv = dev_get_priv(dev);
319 int i, val = 0, offset = 0;
320
321 /*
322 * The TDA998x has a problem when trying to read the EDID close to a
323 * HPD assertion: it needs a delay of 100ms to avoid timing out while
324 * trying to read EDID data.
325 */
326 mdelay(120);
327
328 if (priv->revision == TDA19988)
329 tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM);
330
331 while (offset < buf_size) {
332 tda19988_register_write(priv, REG_DDC_ADDR, 0xa0);
333 tda19988_register_write(priv, REG_DDC_OFFS, offset);
334 tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60);
335 tda19988_register_write(priv, REG_DDC_SEGM, 0);
336
337 /* enable reading EDID */
338 tda19988_register_write(priv, REG_EDID_CTRL, 1);
339
340 /* flags must be cleared by software */
341 tda19988_register_write(priv, REG_EDID_CTRL, 0);
342
343 /* wait for block read to complete */
344 for (i = 300; i > 0; i--) {
345 mdelay(1);
346 val = tda19988_register_read(priv, REG_INT_FLAGS_2);
347 if (val < 0)
348 return val;
349 if (val & INT_FLAGS_2_EDID_BLK_RD)
350 break;
351 }
352
353 if (i == 0)
354 return -ETIMEDOUT;
355
356 priv->current_page = REG2PAGE(REG_EDID_DATA_0);
357 dm_i2c_reg_write(priv->chip,
358 REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0));
359 val = dm_i2c_read(priv->chip,
360 REG2ADDR(REG_EDID_DATA_0), buf + offset, 128);
361 offset += 128;
362 }
363
364 if (priv->revision == TDA19988)
365 tda19988_register_set(priv, REG_TX4, TX4_PD_RAM);
366
367 return offset;
368 }
369
tda19988_enable(struct udevice * dev,int panel_bpp,const struct display_timing * timing)370 static int tda19988_enable(struct udevice *dev, int panel_bpp,
371 const struct display_timing *timing)
372 {
373 struct tda19988_priv *priv = dev_get_priv(dev);
374 u8 div = 148500000 / timing->pixelclock.typ, reg;
375 u16 line_clocks, lines;
376
377 if (dev != 0) {
378 div--;
379 if (div > 3)
380 div = 3;
381 }
382 /* first disable the video ports */
383 tda19988_register_write(priv, REG_ENA_VP_0, 0);
384 tda19988_register_write(priv, REG_ENA_VP_1, 0);
385 tda19988_register_write(priv, REG_ENA_VP_2, 0);
386
387 /* shutdown audio */
388 tda19988_register_write(priv, REG_ENA_AP, 0);
389
390 line_clocks = timing->hsync_len.typ + timing->hback_porch.typ +
391 timing->hactive.typ + timing->hfront_porch.typ;
392 lines = timing->vsync_len.typ + timing->vback_porch.typ +
393 timing->vactive.typ + timing->vfront_porch.typ;
394
395 /* mute the audio FIFO */
396 tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
397 /* HDMI HDCP: off */
398 tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
399 tda19988_register_clear(priv, REG_TX33, TX33_HDMI);
400 tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
401
402 /* no pre-filter or interpolator */
403 tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
404 HVF_CNTRL_0_INTPOL(0));
405 tda19988_register_set(priv, REG_FEAT_POWERDOWN,
406 FEAT_POWERDOWN_PREFILT);
407 tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
408 tda19988_register_write(priv, REG_VIP_CNTRL_4,
409 VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) |
410 VIP_CNTRL_4_TST_PAT);
411
412 tda19988_register_clear(priv, REG_PLL_SERIAL_1,
413 PLL_SERIAL_1_SRL_MAN_IZ);
414 tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
415 PLL_SERIAL_3_SRL_DE);
416
417 tda19988_register_write(priv, REG_SERIALIZER, 0);
418 tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
419
420 tda19988_register_write(priv, REG_RPT_CNTRL, 0);
421 tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
422 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
423 tda19988_register_write(priv, REG_PLL_SERIAL_2,
424 PLL_SERIAL_2_SRL_NOSC(div) |
425 PLL_SERIAL_2_SRL_PR(0));
426
427 /* set color matrix bypass flag: */
428 tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
429 MAT_CONTRL_MAT_SC(1));
430 tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
431
432 /* set BIAS tmds value: */
433 tda19988_register_write(priv, REG_ANA_GENERAL, 0x09);
434
435 /*
436 * Sync on rising HSYNC/VSYNC
437 */
438 reg = VIP_CNTRL_3_SYNC_HS;
439
440 /*
441 * TDA19988 requires high-active sync at input stage,
442 * so invert low-active sync provided by master encoder here
443 */
444 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
445 reg |= VIP_CNTRL_3_H_TGL;
446 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
447 reg |= VIP_CNTRL_3_V_TGL;
448 tda19988_register_write(priv, REG_VIP_CNTRL_3, reg);
449
450 tda19988_register_write(priv, REG_VIDFORMAT, 0x00);
451 tda19988_register_write16(priv, REG_REFPIX_MSB,
452 timing->hfront_porch.typ + 3);
453 tda19988_register_write16(priv, REG_REFLINE_MSB,
454 timing->vfront_porch.typ + 1);
455 tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks);
456 tda19988_register_write16(priv, REG_NLINE_MSB, lines);
457 tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB,
458 timing->vfront_porch.typ);
459 tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB,
460 timing->hfront_porch.typ);
461 tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB,
462 timing->vfront_porch.typ +
463 timing->vsync_len.typ);
464 tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB,
465 timing->hfront_porch.typ);
466 tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0);
467 tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0);
468 tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0);
469 tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0);
470 tda19988_register_write16(priv, REG_HS_PIX_START_MSB,
471 timing->hfront_porch.typ);
472 tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB,
473 timing->hfront_porch.typ +
474 timing->hsync_len.typ);
475 tda19988_register_write16(priv, REG_VWIN_START_1_MSB,
476 lines - timing->vactive.typ - 1);
477 tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1);
478 tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0);
479 tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0);
480 tda19988_register_write16(priv, REG_DE_START_MSB,
481 line_clocks - timing->hactive.typ);
482 tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks);
483
484 if (priv->revision == TDA19988) {
485 /* let incoming pixels fill the active space (if any) */
486 tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00);
487 }
488
489 /*
490 * Always generate sync polarity relative to input sync and
491 * revert input stage toggled sync at output stage
492 */
493 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
494 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
495 reg |= TBG_CNTRL_1_H_TGL;
496 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
497 reg |= TBG_CNTRL_1_V_TGL;
498 tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
499
500 /* must be last register set: */
501 tda19988_register_write(priv, REG_TBG_CNTRL_0, 0);
502
503 /* turn on HDMI HDCP */
504 reg &= ~TBG_CNTRL_1_DWIN_DIS;
505 tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
506 tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
507 tda19988_register_set(priv, REG_TX33, TX33_HDMI);
508
509 mdelay(400);
510
511 /* enable video ports */
512 tda19988_register_write(priv, REG_ENA_VP_0, 0xff);
513 tda19988_register_write(priv, REG_ENA_VP_1, 0xff);
514 tda19988_register_write(priv, REG_ENA_VP_2, 0xff);
515 /* set muxing after enabling ports: */
516 tda19988_register_write(priv, REG_VIP_CNTRL_0,
517 VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
518 tda19988_register_write(priv, REG_VIP_CNTRL_1,
519 VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5));
520 tda19988_register_write(priv, REG_VIP_CNTRL_2,
521 VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1));
522
523 return 0;
524 }
525
526 struct dm_display_ops tda19988_ops = {
527 .read_edid = tda19988_read_edid,
528 .enable = tda19988_enable,
529 };
530
531 static const struct udevice_id tda19988_ids[] = {
532 { .compatible = "nxp,tda998x" },
533 { }
534 };
535
tda19988_probe(struct udevice * dev)536 static int tda19988_probe(struct udevice *dev)
537 {
538 u8 cec_addr, chip_addr, rev_lo, rev_hi;
539 int err;
540 struct tda19988_priv *priv = dev_get_priv(dev);
541
542 chip_addr = dev_read_addr(dev);
543 /* CEC I2C address is using TDA19988 I2C address configuration pins */
544 cec_addr = 0x34 + (chip_addr & 0x03);
545
546 err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip);
547 if (err) {
548 printf("cec i2c_get_chip_for_busnum returned %d\n", err);
549 return err;
550 }
551
552 err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip);
553 if (err) {
554 printf("i2c_get_chip_for_busnum returned %d\n", err);
555 return err;
556 }
557
558 priv->current_page = 0xff;
559
560 /* wake up device */
561 dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS,
562 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
563
564 /* reset audio and I2C master */
565 tda19988_register_write(priv, REG_SOFTRESET,
566 SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
567 mdelay(50);
568 tda19988_register_write(priv, REG_SOFTRESET, 0);
569 mdelay(50);
570
571 /* reset transmitter */
572 tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
573 tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
574
575 /* PLL registers common configuration */
576 tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00);
577 tda19988_register_write(priv, REG_PLL_SERIAL_2,
578 PLL_SERIAL_2_SRL_NOSC(1));
579 tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00);
580 tda19988_register_write(priv, REG_SERIALIZER, 0x00);
581 tda19988_register_write(priv, REG_BUFFER_OUT, 0x00);
582 tda19988_register_write(priv, REG_PLL_SCG1, 0x00);
583 tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
584 tda19988_register_write(priv, REG_SEL_CLK,
585 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
586 tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa);
587 tda19988_register_write(priv, REG_PLL_SCGN2, 0x00);
588 tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b);
589 tda19988_register_write(priv, REG_PLL_SCGR2, 0x00);
590 tda19988_register_write(priv, REG_PLL_SCG2, 0x10);
591
592 /* Write the default value MUX register */
593 tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
594
595 /* read version */
596 rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB);
597 rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB);
598
599 /* mask off feature bits */
600 priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30;
601
602 printf("HDMI: ");
603 switch (priv->revision) {
604 case TDA9989N2:
605 printf("TDA9989 n2\n");
606 break;
607 case TDA19989:
608 printf("TDA19989\n");
609 break;
610 case TDA19989N2:
611 printf("TDA19989 n2\n");
612 break;
613 case TDA19988:
614 printf("TDA19988\n");
615 break;
616 default:
617 printf("unknown TDA device: 0x%04x\n", priv->revision);
618 return -ENXIO;
619 }
620
621 /* after reset, enable DDC */
622 tda19988_register_write(priv, REG_DDC_DISABLE, 0x00);
623
624 /* set clock on DDC channel */
625 tda19988_register_write(priv, REG_TX3, 39);
626
627 /* if necessary, disable multi-master */
628 if (priv->revision == TDA19989)
629 tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
630
631 dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL,
632 CEC_FRO_IM_CLK_CTRL_GHOST_DIS |
633 CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
634 /* ensure interrupts are disabled */
635 dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0);
636 /* clear pending interrupts */
637 dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT);
638 tda19988_register_read(priv, REG_INT_FLAGS_0);
639 tda19988_register_read(priv, REG_INT_FLAGS_1);
640 tda19988_register_read(priv, REG_INT_FLAGS_2);
641
642 /* enable EDID read irq */
643 tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
644
645 return 0;
646 }
647
648 U_BOOT_DRIVER(tda19988) = {
649 .name = "tda19988",
650 .id = UCLASS_DISPLAY,
651 .of_match = tda19988_ids,
652 .ops = &tda19988_ops,
653 .probe = tda19988_probe,
654 .priv_auto = sizeof(struct tda19988_priv),
655 };
656