| /u-boot/board/freescale/lx2160a/ |
| A D | README | 90 |Connect I/O cable to IO_SLOT1(J110)
93 |Connect I/O cable to IO_SLOT2(J113)
97 |Connect I/O cable to IO_SLOT1(J110)
100 |Connect I/O cable to IO_SLOT2(J113)
104 |Connect I/O cable to IO_SLOT1(J110)
107 |Connect I/O cable to IO_SLOT2(J113)
111 |Connect I/O cable to IO_SLOT1(J110)
114 |Connect I/O cable to IO_SLOT2(J113)
118 |Connect I/O cable to IO_SLOT1(J110)
139 |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
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| /u-boot/doc/chromium/devkeys/ |
| A D | kernel.keyblock | 3 …I}&E�8Kf�\,����� {#�� 2�#�+rאSR���r�p<�'B�+T��a�Ԩ���=�ކ���(^ڴG���I�c�B � �l���4��D�z�a…
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| /u-boot/doc/ |
| A D | README.mpc85xx | 51 Properties : 256K, AS0, I, IPROT
57 Properties : 1M, AS1, I, G, IPROT
69 Properties : 1M, AS1, I, G
98 Properties : 1M, AS1, I, G, IPROT
101 Properties : 4M, AS0, I, G, IPROT
109 Properties : 1M, AS1, I, G, IPROT
112 Properties : 4M, AS1, I, G, IPROT
125 Properties : 1M, AS1, I, G
131 Properties : 1M, AS1, I
137 Properties : 4M, AS1, I, G, IPROT
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| A D | README.generic-board | 58 5. While it is a bit of a tricky change, I believe it is worthwhile and
88 I think it is a good target for this series. On the other hand, x86 is
91 After a suggestion from Wolfgang I have added PPC also. This is the
101 for now I have judged that to be counter-productive.
104 be accessing it. I have done this in the same way as global_data and the
108 to pre-relocation init functions. I think this makes sense, but it can
113 unification of the board init code. So I hope we can address issues with
117 I have run-tested ARM on Tegra Seaboard only. To try it out, define
122 I have run this though MAKEALL with CONFIG_SYS_GENERIC_BOARD on for all
124 the board config, which I have sent patches for. The main issue is
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| A D | README.arm-caches | 1 Disabling I-cache:
7 Enabling I-cache:
14 - Implement enable_caches() for your platform and enable the I-cache and
47 - cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
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| /u-boot/arch/arm/dts/ |
| A D | stm32h7-u-boot.dtsi | 194 <STM32_PINMUX('I', 0, AF12)>,
195 <STM32_PINMUX('I', 1, AF12)>,
196 <STM32_PINMUX('I', 2, AF12)>,
197 <STM32_PINMUX('I', 3, AF12)>,
198 <STM32_PINMUX('I', 4, AF12)>,
199 <STM32_PINMUX('I', 5, AF12)>,
200 <STM32_PINMUX('I', 6, AF12)>,
201 <STM32_PINMUX('I', 7, AF12)>,
202 <STM32_PINMUX('I', 9, AF12)>,
203 <STM32_PINMUX('I',10, AF12)>;
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| A D | stm32746g-eval-u-boot.dtsi | 91 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
92 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
93 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
94 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
95 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
96 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
97 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
98 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
125 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
126 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
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| A D | stm32429i-eval-u-boot.dtsi | 153 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
154 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
155 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
156 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
157 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
158 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
159 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
160 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
189 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
190 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
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| A D | stm32f769-disco-u-boot.dtsi | 141 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
142 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
143 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
144 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
145 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
146 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
147 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
148 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
175 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
176 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
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| A D | stm32mp15-pinctrl.dtsi | 90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
563 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
564 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
565 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
570 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
[all …]
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| A D | stm32f469-disco-u-boot.dtsi | 145 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
146 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
147 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
148 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
149 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
150 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
151 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
152 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
181 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
182 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
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| A D | fsl-lx2160a-qds.dtsi | 182 emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
189 emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
196 emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
203 emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
210 emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
217 emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
224 emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
231 emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
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| /u-boot/board/avionic-design/common/ |
| A D | tamonten.c | 25 gpio_request(TEGRA_GPIO(I, 4), NULL); in gpio_early_init()
26 gpio_direction_output(TEGRA_GPIO(I, 4), 1); in gpio_early_init()
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| A D | tamonten-ng.c | 49 gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH"); in gpio_early_init()
50 gpio_direction_output(TEGRA_GPIO(I, 4), 1); in gpio_early_init()
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| /u-boot/board/nvidia/seaboard/ |
| A D | seaboard.c | 23 gpio_request(TEGRA_GPIO(I, 3), "uart_en"); in gpio_early_init_uart()
24 gpio_direction_output(TEGRA_GPIO(I, 3), 0); in gpio_early_init_uart()
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| /u-boot/arch/arm/mach-tegra/tegra210/ |
| A D | Kconfig | 18 P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
28 to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD
36 P2571 is a P2530 married to a P1963 I/O board
42 P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
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| /u-boot/scripts/coccinelle/iterators/ |
| A D | itnull.cocci | 22 iterator I;
27 I(x,...) { <...
65 iterator I;
70 *I@p1(x,...)
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| /u-boot/arch/arm/cpu/arm1136/ |
| A D | start.S | 81 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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| /u-boot/arch/arc/lib/ |
| A D | start.S | 15 ; Disable/enable I-cache according to configuration
17 breq r5, 0, 1f ; I$ doesn't exist
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| /u-boot/arch/arm/cpu/arm1176/ |
| A D | start.S | 87 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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| /u-boot/lib/ |
| A D | sha512.c | 131 static inline void LOAD_OP(int I, uint64_t *W, const uint8_t *input) in LOAD_OP() argument
133 GET_UINT64_BE(W[I], input, I*8); in LOAD_OP()
136 static inline void BLEND_OP(int I, uint64_t *W) in BLEND_OP() argument
138 W[I & 15] += s1(W[(I-2) & 15]) + W[(I-7) & 15] + s0(W[(I-15) & 15]); in BLEND_OP()
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| /u-boot/tools/binman/test/files/ |
| A D | 1.dat | 1 sorry I'm late
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| A D | 2.dat | 1 Oh, don't bother apologising, I'm sorry you're alive
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| /u-boot/arch/arm/cpu/arm920t/ |
| A D | start.S | 97 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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| /u-boot/arch/powerpc/dts/ |
| A D | p1020rdb-pc.dts | 24 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
30 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
|