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Searched refs:I2C2_BASE_ADDR (Results 1 – 18 of 18) sorted by relevance

/u-boot/arch/arm/include/asm/arch-stv0991/
A Dhardware.h51 #define I2C2_BASE_ADDR 0x80402000UL macro
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dconfig.h53 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) macro
/u-boot/arch/arm/mach-imx/
A Di2c-mxv7.c66 (void *)I2C2_BASE_ADDR,
/u-boot/drivers/i2c/
A Dmxc_i2c.c346 #if !defined(I2C2_BASE_ADDR)
347 #define I2C2_BASE_ADDR 0 macro
378 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
387 { 1, I2C2_BASE_ADDR, 0 },
/u-boot/arch/arm/mach-imx/mx6/
A Dmodule_fuse.c297 case I2C2_BASE_ADDR: in i2c_fused()
/u-boot/arch/arm/include/asm/arch-mx35/
A Dimx-regs.h34 #define I2C2_BASE_ADDR 0x43F98000 macro
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dsoc.c339 #ifdef I2C2_BASE_ADDR in erratum_a009203()
340 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); in erratum_a009203()
/u-boot/arch/arm/include/asm/arch-s32v234/
A Dimx-regs.h88 #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000) macro
/u-boot/arch/arm/include/asm/arch-mx25/
A Dimx-regs.h289 #define I2C2_BASE_ADDR (0x43F98000) macro
/u-boot/arch/arm/include/asm/arch-mx27/
A Dimx-regs.h192 #define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) macro
/u-boot/arch/arm/include/asm/arch-mx5/
A Dimx-regs.h108 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) macro
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dimmap_lsch3.h59 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) macro
A Dimmap_lsch2.h77 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) macro
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dimx-regs.h42 #define I2C2_BASE_ADDR 0x30A30000 macro
/u-boot/arch/arm/include/asm/arch-vf610/
A Dimx-regs.h78 #define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000) macro
/u-boot/arch/arm/include/asm/arch-mx31/
A Dimx-regs.h603 #define I2C2_BASE_ADDR 0x43F98000 macro
/u-boot/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h264 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) macro
/u-boot/arch/arm/include/asm/arch-mx7/
A Dimx-regs.h174 #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) macro

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