Home
last modified time | relevance | path

Searched refs:ICPU_GPR (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h416 writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6)); in hal_vcoreiii_ddr_failed()
810 writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7)); in hal_vcoreiii_init_memctl()
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h11 #define ICPU_GPR(x) (0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h10 #define ICPU_GPR(x) (0x4 * (x)) macro

Completed in 16 milliseconds