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Searched refs:ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h78 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h89 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h87 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h95 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h92 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h489 val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA; in hal_vcoreiii_ddr_verified()

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