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Searched refs:ICPU_MEMCTRL_DQS_DLY (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h337 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
346 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in incr_dly()
349 writel(r + 1, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in incr_dly()
358 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); in adjust_dly()
361 writel(r + adjust, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); in adjust_dly()
371 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)) - start; in center_dly()
373 writel(start + (r >> 1), BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in center_dly()
590 dqs_s = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in hal_vcoreiii_train_bytelane()
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h207 #define ICPU_MEMCTRL_DQS_DLY(x) (0x270) macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h218 #define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h244 #define ICPU_MEMCTRL_DQS_DLY(x) (0x148 + 0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h252 #define ICPU_MEMCTRL_DQS_DLY(x) (0x170 + 0x4 * (x)) macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h249 #define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x)) macro

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