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Searched refs:ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0 (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h213 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h225 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h251 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h259 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h256 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) macro

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