ICPU_MEMCTRL_TIMING0 (reference) in projects: u-boot

Searched refs:ICPU_MEMCTRL_TIMING0 (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/
A D	ddr.h	`784 writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0); in hal_vcoreiii_init_memctl() 786 clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1)); in hal_vcoreiii_init_memctl() 787 setbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, MSCC_MEMPARM_TIMING0); in hal_vcoreiii_init_memctl()`
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A D	luton_icpu_cfg.h	`109 #define ICPU_MEMCTRL_TIMING0 0x248 macro`
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A D	ocelot_icpu_cfg.h	`120 #define ICPU_MEMCTRL_TIMING0 0x124 macro`
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A D	serval_icpu_cfg.h	`123 #define ICPU_MEMCTRL_TIMING0 0x11c macro`
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A D	jr2_icpu_cfg.h	`131 #define ICPU_MEMCTRL_TIMING0 0x144 macro`
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A D	servalt_icpu_cfg.h	`128 #define ICPU_MEMCTRL_TIMING0 0x124 macro`

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