ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY (reference) in projects: u-boot

Searched refs:ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/luton/
A D	luton_icpu_cfg.h	`111 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A D	ocelot_icpu_cfg.h	`122 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A D	serval_icpu_cfg.h	`125 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A D	jr2_icpu_cfg.h	`133 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A D	servalt_icpu_cfg.h	`130 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/
A D	ddr.h	`251 ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \`

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