ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY (reference) in projects: u-boot

Searched refs:ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/
A D	ddr.h	`269 ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL + \ 306 ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \`
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A D	luton_icpu_cfg.h	`152 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A D	ocelot_icpu_cfg.h	`163 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A D	serval_icpu_cfg.h	`166 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A D	jr2_icpu_cfg.h	`174 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A D	servalt_icpu_cfg.h	`171 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) macro`

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