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Searched refs:ICPU_MEMCTRL_TIMING2 (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h155 #define ICPU_MEMCTRL_TIMING2 0x250 macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h166 #define ICPU_MEMCTRL_TIMING2 0x12c macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h169 #define ICPU_MEMCTRL_TIMING2 0x124 macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h177 #define ICPU_MEMCTRL_TIMING2 0x14c macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h174 #define ICPU_MEMCTRL_TIMING2 0x12c macro
/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h791 writel(MSCC_MEMPARM_TIMING2, BASE_CFG + ICPU_MEMCTRL_TIMING2); in hal_vcoreiii_init_memctl()

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