ICPU_MEMCTRL_TIMING2_INIT_DLY (reference) in projects: u-boot

Searched refs:ICPU_MEMCTRL_TIMING2_INIT_DLY (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A D	ocelot_icpu_cfg.h	`177 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A D	serval_icpu_cfg.h	`180 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A D	jr2_icpu_cfg.h	`188 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A D	servalt_icpu_cfg.h	`185 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro`
/u-boot/arch/mips/mach-mscc/include/mach/
A D	ddr.h	`277 ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1)`

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