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Searched refs:ICPU_MEMPHY_CFG_PHY_RST (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h470 ICPU_MEMPHY_CFG_PHY_RST, BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_reset_assert()
651 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_RST); in hal_vcoreiii_ddr_reset_assert()
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_icpu_cfg.h231 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_icpu_cfg.h243 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_icpu_cfg.h282 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_icpu_cfg.h290 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_icpu_cfg.h287 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro

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