| /u-boot/doc/ |
| A D | README.fsl-esdhc | 4 ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
5 determined by ESDHC IP's endian mode or processor's endian mode.
7 ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
8 by ESDHC IP's endian mode or processor's endian mode.
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| A D | README.SNTP | 6 parameter of server's IP address or environment variable
11 If the DHCP server provides time server's IP or time offset, you
16 2. Only the 1st NTP server IP, in the option ntp-servers of DHCP, will
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| A D | README.mxc_ocotp | 4 This IP can be found on the following SoCs:
8 Note that this IP is different from albeit similar to the IPs of the same name
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| A D | README.fuse | 14 fusebox control IP registers. This is limited to 32 bits with the current API.
19 Upon startup, the fusebox control IP reads the fuse values and stores them to a
43 each IP.
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| A D | README.dns | 11 Internet by translating human-friendly computer hostnames into IP addresses.
31 By default, dns does nothing except print the IP number on
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| /u-boot/drivers/spi/ |
| A D | Kconfig | 50 IP core. Please find details on the "Embedded Peripherals IP
122 Cadence IP core.
141 IP core.
148 Exynos IP core.
164 Freescale IP core.
179 ICH IP core.
250 Marvell IP core.
376 this ST IP core.
391 IP core.
445 SPI IP core.
[all …]
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| /u-boot/doc/usage/ |
| A D | netconsole.rst | 14 We use an environment variable 'ncip' to set the IP address and the
17 broadcast address and port 6666 are used. If it is set to an IP
23 For example, if your server IP is 192.168.1.1, you could use::
37 specify the target IP address (or host name, assuming DNS is working). The
53 Minimally, the host IP address needs to be specified. This can be
73 source IP to use (defaults to the interface's address)
82 IP address for logging agent (this is the required parameter)
97 the respective Ethernet interface has to be brought up using the "IP
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| /u-boot/net/ |
| A D | Kconfig | 42 bool "Support IP datagram reassembly"
45 Selecting this will enable IP datagram reassembly according
49 int "Size of buffer used for IP datagram reassembly"
56 IP datagrams that can be received.
81 while IP is obtained from main DHCP server.
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| /u-boot/drivers/phy/rockchip/ |
| A D | Kconfig | 12 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
25 Support for Rockchip PCIe3 PHY with Synopsys IP block.
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| /u-boot/drivers/axi/ |
| A D | Kconfig | 7 communication with IP cores in Xilinx FPGAs).
23 IP cores in the FPGA (e.g. video transmitter cores).
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| /u-boot/drivers/bios_emulator/include/x86emu/ |
| A D | regs.h | 104 i386_general_register SP, BP, SI, DI, IP; member
151 #define R_IP spc.IP.I16_reg.x_reg
159 #define R_IP spc.IP.I16_reg.x_reg
167 #define R_EIP spc.IP.I32_reg.e_reg
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| /u-boot/doc/device-tree-bindings/reset/ |
| A D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
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| /u-boot/doc/device-tree-bindings/pwm/ |
| A D | pwm-sifive.txt | 7 PWM RTL that corresponds to the IP block version numbers can be found
16 SiFive PWM v0 IP block with no chip integration tweaks.
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| /u-boot/doc/device-tree-bindings/net/ |
| A D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
4 IP block. The IP supports multiple options for bus type, clocking and reset
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
14 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
22 - clock-names: May contain any/all of the following depending on the IP
56 Note: Support for additional IP configurations may require adding the
89 - reset-names: May contain any/all of the following depending on the IP
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| /u-boot/drivers/usb/musb-new/ |
| A D | Kconfig | 27 silicon IP.
37 silicon IP.
56 if it is available on your Mediatek MUSB IP based platform.
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| /u-boot/drivers/clk/sifive/ |
| A D | Kconfig | 14 Supports the Power Reset Clock interface (PRCI) IP block found in
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| /u-boot/doc/device-tree-bindings/pci_endpoint/ |
| A D | cdns,cdns-pcie-ep.txt | 4 - compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
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| /u-boot/doc/device-tree-bindings/axi/ |
| A D | gdsys,ihs_axi.txt | 4 the connected devices (usually IP cores) can be controlled via software.
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| /u-boot/drivers/usb/dwc3/ |
| A D | Kconfig | 6 USB controller based on the DesignWare USB3 IP Core.
22 AM437x use this IP for USB2/3 functionality.
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
42 drivers of the RCC IP, macros are available to generate the index in
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| /u-boot/doc/device-tree-bindings/misc/ |
| A D | esm-k3.txt | 4 ESM (Error Signaling Module) is an IP block on TI K3 devices that allows
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| /u-boot/doc/device-tree-bindings/timer/ |
| A D | atcpit100_timer.txt | 3 ATCPIT100 is a generic IP block from Andes Technology, embedded in
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| /u-boot/doc/device-tree-bindings/thermal/ |
| A D | ti_soc_thermal.txt | 7 circuits and other analog IP blocks. The analog-to-digital
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| /u-boot/doc/device-tree-bindings/sound/ |
| A D | snow.txt | 18 string) and the second entry must be the phandle of the HDMI IP block node
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| /u-boot/drivers/usb/mtu3/ |
| A D | Kconfig | 3 # For MTK USB3.0 IP
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