IRTL_1024_NS (reference) in projects: u-boot

Searched refs:IRTL_1024_NS (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/x86/cpu/broadwell/
A D	cpu_full.c	443 msr.lo = IRTL_VALID \| IRTL_1024_NS \| C_STATE_LATENCY_CONTROL_0_LIMIT; in configure_c_states() 448 msr.lo = IRTL_VALID \| IRTL_1024_NS \| C_STATE_LATENCY_CONTROL_1_LIMIT; in configure_c_states() 453 msr.lo = IRTL_VALID \| IRTL_1024_NS \| C_STATE_LATENCY_CONTROL_2_LIMIT; in configure_c_states() 458 msr.lo = IRTL_VALID \| IRTL_1024_NS \| C_STATE_LATENCY_CONTROL_3_LIMIT; in configure_c_states() 463 msr.lo = IRTL_VALID \| IRTL_1024_NS \| C_STATE_LATENCY_CONTROL_4_LIMIT; in configure_c_states() 468 msr.lo = IRTL_VALID \| IRTL_1024_NS \| C_STATE_LATENCY_CONTROL_5_LIMIT; in configure_c_states()
/u-boot/arch/x86/include/asm/arch-ivybridge/
A D	model_206ax.h	`35 #define IRTL_1024_NS (2 << 10) macro`
/u-boot/arch/x86/cpu/ivybridge/
A D	model_206ax.c	`255 msr.lo = IRTL_VALID \| IRTL_1024_NS \| 0x50; in configure_c_states() 260 msr.lo = IRTL_VALID \| IRTL_1024_NS \| 0x68; in configure_c_states() 265 msr.lo = IRTL_VALID \| IRTL_1024_NS \| 0x6D; in configure_c_states()`
/u-boot/arch/x86/include/asm/
A D	msr-index.h	`251 #define IRTL_1024_NS (2 << 10) macro`

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