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Searched refs:KS2_DDR3BPLLCTL0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-keystone/
A Dclock.c33 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
318 reg = KS2_DDR3BPLLCTL0; in pll_freq_get()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dhardware.h182 #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) macro

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