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Searched refs:KS2_EDMA0_BASE (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-keystone/
A Dddr3.c182 edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); in ddr3_reset_data()
190 qedma3_start(KS2_EDMA0_BASE, &edma_channel); in ddr3_reset_data()
221 edma3_set_src_addr(KS2_EDMA0_BASE, in ddr3_reset_data()
223 edma3_set_dest_addr(KS2_EDMA0_BASE, in ddr3_reset_data()
226 while (edma3_check_for_transfer(KS2_EDMA0_BASE, in ddr3_reset_data()
232 qedma3_stop(KS2_EDMA0_BASE, &edma_channel); in ddr3_reset_data()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dhardware.h121 #define KS2_EDMA0_BASE 0x02700000 macro

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