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Searched refs:KS2_MAINPLLCTL0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-keystone/
A Dclock.c29 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
290 tmp = __raw_readl(KS2_MAINPLLCTL0); in pll_freq_get()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dhardware.h176 #define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) macro

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