Home
last modified time | relevance | path

Searched refs:L1_CACHE_BYTES (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/powerpc/include/asm/
A Dcache.h20 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
26 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
32 #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
35 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
38 #define SMP_CACHE_BYTES L1_CACHE_BYTES
41 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
44 __attribute__((__aligned__(L1_CACHE_BYTES), \
/u-boot/arch/powerpc/lib/
A Dppccache.S68 li r5,L1_CACHE_BYTES-1
77 addi r3,r3,L1_CACHE_BYTES
92 li r5,L1_CACHE_BYTES-1
102 addi r3,r3,L1_CACHE_BYTES
/u-boot/arch/sh/cpu/sh4/
A Dcache.c62 start &= ~(L1_CACHE_BYTES - 1); in flush_dcache_range()
63 for (v = start; v < end; v += L1_CACHE_BYTES) { in flush_dcache_range()
73 start &= ~(L1_CACHE_BYTES - 1); in invalidate_dcache_range()
74 for (v = start; v < end; v += L1_CACHE_BYTES) { in invalidate_dcache_range()
/u-boot/arch/mips/include/asm/
A Dcache.h10 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
12 #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
/u-boot/arch/sh/include/asm/
A Dcache.h6 #define L1_CACHE_BYTES 32 macro
26 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dconfig.h30 #ifndef L1_CACHE_BYTES
32 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) macro
191 #ifndef L1_CACHE_BYTES
193 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) macro
/u-boot/arch/nios2/include/asm/bitops/
A Datomic.h16 # define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE…
/u-boot/arch/powerpc/cpu/mpc86xx/
A Dcache.S11 # define CACHE_LINE_SIZE L1_CACHE_BYTES

Completed in 10 milliseconds