| /u-boot/doc/device-tree-bindings/arm/ |
| A D | l2c2x0.txt | 1 * ARM L2 Cache Controller
5 of the L2 cache controller have compatible programming models (Note 1).
10 The ARM L2 cache representation in the device tree should be done as follows:
20 offset needs to be added to the address before passing down to the L2
24 maintenance operations on L1 are broadcasted to the L2 and L2
60 - wt-override: If present then L2 is forced to Write through mode
87 - arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
90 - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
99 L2: cache-controller {
110 Note 1: The description in this document doesn't apply to integrated L2
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| /u-boot/arch/arm/dts/ |
| A D | vexpress-v2p-ca9.dts | 42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
164 L2: cache-controller@1e00a000 { label
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
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| A D | vexpress-v2p-ca5s.dts | 42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
130 L2: cache-controller@2c0f0000 { label
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| A D | imx6q.dtsi | 24 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
93 next-level-cache = <&L2>;
127 next-level-cache = <&L2>;
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| A D | socfpga_arria10-u-boot.dtsi | 76 &L2 {
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| A D | imx6dl.dtsi | 22 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
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| A D | rk3188.dtsi | 23 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
54 next-level-cache = <&L2>;
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| A D | armada-xp-crs328-4c-20s-4s.dtsi | 43 &L2 {
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| A D | armada-xp-crs305-1g-4s.dtsi | 43 &L2 {
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| A D | armada-xp-crs326-24g-2s.dtsi | 43 &L2 {
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| /u-boot/doc/ |
| A D | README.mpc74xx | 10 There is a framework in place to enable the L2 cache, and to program
12 sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be
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| /u-boot/arch/riscv/dts/ |
| A D | ae350_32.dts | 37 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
79 next-level-cache = <&L2>;
100 next-level-cache = <&L2>;
109 L2: l2-cache@e0500000 { label
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| A D | ae350_64.dts | 37 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
79 next-level-cache = <&L2>;
100 next-level-cache = <&L2>;
109 L2: l2-cache@e0500000 { label
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| /u-boot/doc/device-tree-bindings/rtc/ |
| A D | brcm,brcmstb-waketimer.txt | 10 - interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
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| /u-boot/arch/arm/mach-uniphier/ |
| A D | Kconfig | 77 bool "Enable the UniPhier L2 cache controller"
82 This option allows to use the UniPhier System Cache as L2 cache.
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| /u-boot/arch/powerpc/dts/ |
| A D | socrates.dts | 40 next-level-cache = <&L2>;
78 L2: l2-cache-controller@20000 { label
82 cache-size = <0x40000>; // L2, 256K
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| /u-boot/drivers/cache/ |
| A D | Kconfig | 32 device tree and enable L2 cache.
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| /u-boot/arch/arm/mach-rockchip/ |
| A D | Kconfig | 67 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
127 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
175 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
196 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
255 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| A D | README.soc | 17 processor cores with datapath acceleration optimized for L2/3 packet
23 - 1 MB unified L2 Cache
66 - 1MB L2 - Cache per cluster
133 ECC protected L2 cache.
173 processor cores with datapath acceleration optimized for L2/3 packet
179 - 2 MB unified L2 Cache
263 d) No L2 switch
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| /u-boot/arch/x86/cpu/intel_common/ |
| A D | car2.S | 254 #error "CQOS CAR may not use whole L2 cache area"
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| /u-boot/board/keymile/km_arm/ |
| A D | kwbimage.cfg | 35 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
36 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
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| /u-boot/board/raidsonic/ib62x0/ |
| A D | kwbimage.cfg | 149 DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
150 DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | README | 23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
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| /u-boot/board/freescale/ls1021aqds/ |
| A D | README | 23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
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| /u-boot/arch/x86/include/asm/arch-braswell/ |
| A D | gpio.h | 33 L2, enumerator
|