Searched refs:L2CSR0_L2PE (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
A D	start.S	698 lis r4, (L2CSR0_L2PE)@h 699 ori r4, r4, (L2CSR0_L2PE)@l 710 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
A D	cpu_init.c	573 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); in enable_cluster_l2()
/u-boot/arch/powerpc/include/asm/
A D	processor.h	502 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ macro

Completed in 12 milliseconds

Last Index update Fri Sep 05 17:56:23 CST 2025