Searched refs:L3 (Results 1 – 9 of 9) sorted by relevance
51 /* L3 to L4 ABE mapping */108 <0x49022000 0xff>; /* L3 Interconnect */141 <0x49024000 0xff>; /* L3 Interconnect */174 <0x49026000 0xff>; /* L3 Interconnect */226 <0x4902e000 0x7f>; /* L3 Interconnect */269 <0x49032000 0x7f>; /* L3 Interconnect */
51 /* L3 to L4 ABE mapping */108 <0x49022000 0xff>; /* L3 Interconnect */141 <0x49024000 0xff>; /* L3 Interconnect */174 <0x49026000 0xff>; /* L3 Interconnect */242 <0x4902e000 0x7f>; /* L3 Interconnect */304 <0x49032000 0x7f>; /* L3 Interconnect */
244 <0x4902c000 0x4902c000 0x1000>; /* L3 */
1532 /* Unused DSS L4 access, see L3 instead */
34 L3, enumerator
268 hex "Size in bytes of the L3 SRAM reserved by ROM to store data"272 the public L3 OCMC RAM to store r/w data like stack,
46 - 256 KB shared L3 CoreNet platform cache (CPC)
19 - 256 KB shared L3 CoreNet platform cache (CPC)
57 * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
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