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Searched refs:LPDDR2 (Results 1 – 16 of 16) sorted by relevance

/u-boot/board/freescale/mx6memcal/
A DKconfig88 Select the type of DDR (DDR3 or LPDDR2) used on your design
95 config LPDDR2 config in mx6memcal specifics""choicef565d0e00304
96 bool "LPDDR2"
98 Select this if your board design uses LPDDR2.
122 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
123 depends on LPDDR2
126 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
127 depends on LPDDR2
A DREADME35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
/u-boot/drivers/ram/rockchip/
A DKconfig33 bool "LPDDR2 support for Rockchip PX30"
36 This enables LPDDR2 sdram support instead of the default DDR3 support
A Dsdram-px30-lpddr2-detect-333.inc28 .dramtype = LPDDR2,
A Dsdram_common.c23 case LPDDR2: in sdram_print_dram_type()
294 } else if (dram_type == LPDDR3 || dram_type == LPDDR2) { in sdram_detect_dbw()
A Dsdram_px30.c295 sdram_params->base.dramtype == LPDDR2) && in set_ctl_address_map()
539 } else if (sdram_params->base.dramtype == LPDDR2) { in sdram_init_()
589 if (dram_type == LPDDR2) in dram_detect_cap()
A Dsdram_phy_px30.c66 if (dram_type == LPDDR2) in sdram_phy_set_ds_odt()
A Dsdram_rk322x.c448 if (dramtype == LPDDR2) { in pctl_cfg()
490 case LPDDR2: in phy_cfg()
504 if (sdram_params->base.dramtype == LPDDR2) in phy_cfg()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram.h12 LPDDR2 = 0x5, enumerator
/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32mp1-ddr.txt1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
/u-boot/drivers/ram/stm32mp1/
A DKconfig10 family: support for LPDDR2, LPDDR3 and DDR3
/u-boot/arch/arm/mach-socfpga/
A Dwrap_sdram_config.c236 #error LPDDR2 and other DRAM types are not yet supported
/u-boot/board/freescale/mx6qarm2/
A Dimximage_mx6dl.cfg148 /*LPDDR2 ZQ params */
192 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
/u-boot/board/ccv/xpress/
A Dimximage.cfg145 * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
/u-boot/arch/arm/mach-at91/
A DKconfig212 processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM
/u-boot/drivers/power/
A DKconfig193 On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
197 LPDDR2, and the codec. It should be 1.8V.

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