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Searched refs:LRADC_CTRL1_LRADC7_IRQ (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dspl_lradc_init.c53 writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr); in mxs_lradc_enable_batt_measurement()
/u-boot/arch/arm/include/asm/arch-mxs/
A Dregs-lradc.h80 #define LRADC_CTRL1_LRADC7_IRQ (1 << 7) macro

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